CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 14

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Audio is supported by an internal controller, designed to
connect to multiple AC97 compatible codecs. An IR (infra-
red) port supports all popular IR communication protocols.
The IR port is shared with one of two industry-standard
serial ports that can reach speeds of 115.2 kbps. An LPC
(low pin count) port is provided to facilitate connections to a
SuperI/O should additional expansion, such as a floppy
drive, be necessary, and/or to an LPC ROM for the system
BIOS.
The hard disk controller is an ATA-5 compatible bus mas-
tering IDE controller; includes support for two ATA-compli-
ant devices on one channel. Two dual-port USBs
(universal serial buses, USB specification v1.1 compliant)
provide four ports with both low and full-speed capabilities
for Plug & Play expansion for a variety of consumer periph-
eral devices such as a keyboard, mouse, printer, and digi-
tal camera. A battery-backed RTC (real-time clock) keeps
track of time and provides calendar functions.
A suite of 82xx devices provide the legacy PC functionality
required by most designs, including two PICs (programma-
ble interrupt controllers), one PIT (programmable interval
timer) with three channels, and DMA (direct memory
access) functions. The Geode CS5535 companion device
contains eight MFGPTs (multi-function general purpose
timers) that can be used for a variety of functions. A num-
ber of GPIOs (general purpose input/outputs) are provided,
and are assigned to system functions on power-up (i.e.,
LPC port); each of these may be reassigned and given dif-
ferent I/O characteristics such as debounce, edge-trigger-
ing, etc.
State-of-the-art power management features are attained
with the division of the device into two internal power
domains. The GPIOs and multi-function timers are distrib-
uted into each of the two domains to allow these to act as
wakeup sources for the device. In addition to full ACPI
(Advanced Configuration Power Interface) compliance and
support of industry-standard Wakeup and Sleep modes,
the device automatically disables clocks from internal
blocks when they are not being used.
1.2
General Features
14
Designed for use with AMD’s Geode GX processor
208-Terminal PBGA (plastic ball grid array) package
3.3V I/O and 1.2V or 1.5V (nominal) Core operation
Low power operation: 150 mW Typ in Working state
Working and Standby power domains
IEEE 1149.1 compliant TAP and boundary scan
Features
31506B
GeodeLink™ PCI Bridge (South Bridge)
GeodeLink™ Control Processor
ATA-5 Controller
Flash Interface
Provides a PCI interface for GeodeLink devices:
— PCI specification v2.2 compliant
— 32-Bit, 33/66 MHz operation
— Transaction FIFOs (first in/first out)
— Bus master or slave
— Converts selected PCI configuration bus cycles to
— Capable of handling in-bound transactions immedi-
— Mapping of PCI virtual configuration space to MSR
— Serialized processor control interface
SUSP#/SUPA# handshake with power management
logic provides Sleep control of all GeodeLink devices
System software debug support using built-in “logic
analyzer” with:
— 8192-bit capture memory
— Capture memory can be organized wide or narrow
— “Analyzer” can be connected to thousands of
— Synchronous operation with Geode GX processor
— JTAG interface and system bus interfaces
— For debug use, able to conduct any GeodeLink trans-
— Manufacturing test support
66 MB per second IDE Controller in UDMA mode per
the ATA-5 specification
3.3V interface
Legacy and Enhanced PIO (Programmable I/O),
MDMA (Multi DMA), and UDMA (Ultra DMA) modes
One channel with two devices
Multiplexed with Flash interface
Multiplexed with IDE interface
Connects to array of industry standard NAND Flash
and/or NOR Flash
NOR optional execute-in-place boot source
NAND optional file system
General purpose ISA bus slave-like devices supported
with configurable chip selects
Hardware support for SmartMedia type ECC (Error
Correcting Code) calculation off loading software inten-
sive algorithm
internal MSR (Model Specific Register) cycles
ately after reset - no setup
space is done completely in Virtual System Architec-
ture™ (VSA) code
possible internal nodes
GeodeLink Control Processor
action via the JTAG interface
AMD Geode™ CS5535 Companion Device Data Book
Overview