CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 86

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.2.7
If the HCD (Hold for CIS Transfer Disable) bit in
GLPCI_MSR_CTRL (MSR 51000010h[9]) is set, any in-
bound memory, I/O, or external MSR read/write response
packet will be checked for SSMI and EXCEP bits. If the
response packet has the EXCEP bit and/or SSMI bit set,
then the GLPCI_SB will not complete the transaction (it will
either issue a Retry or Hold PCI bus) until the CIS transfer
completes.
During an out-bound transaction, when the GLPCI_SB
issues a Master Abort, the EXCEP bit in the GLIU
response packet is set.
5.2.8
If the SDOFF (Subtractive Decode Off) bit in the
GLPCI_MSR_CTRL (MSR 51000010h[10]) is cleared
(reset value), any PCI transaction, other than Configuration
Read/Write, Interrupt Acknowledge, and Special Cycle
transactions, not claimed by any device (i.e., not asserting
DEVSEL#) within the default active decode cycles (three
cycles immediately after FRAME# being asserted) will be
accepted by GLPCI_SB at the fourth clock edge. The Retry
condition will be issued for Memory Read, Memory Read
Line, Memory Read Multiple (after Initial Latency Timeout),
and I/O Read/Write (immediately) and all the required infor-
mation (command, address and byte enable bits) is stored
for the following Delayed Transactions. During Delayed
Transactions, the active decode scheme is used. Any
address accessed through a subtractive decoding is
assumed to be non-prefetchable.
5.2.9
In any in-bound I/O transaction, the byte enables BE[3:0]#
are checked against address bits PCI_AD[1:0] for valid
combinations. If an illegal byte enable pattern is asserted,
the GLPCI_SB will issue a Target Abort. The only excep-
tion is when subtractive decode is used. During a subtrac-
tive decode, PCI_AD[1:0] and BE# are passed to the GLIU
as is. The IOED (I/O Addressing Error Checking Disable)
bit in GLPCI_MSR_CTRL (MSR 51000010h[8]) can be set
to disable the I/O addressing error checking, where AD[1:0]
is ignored and the byte enables are passed to the GLIU.
5.2.10
This algorithm issues multiple four byte reads to the IDE
data register (1F0h) at the “beginning” of an IDE “read
operation”. The hardware continues to read ahead of soft-
ware read requests until a sector boundary is about to be
crossed. The hardware does not read ahead over a sector
boundary. Once a software read crosses a sector bound-
ary, the hardware proceeds to read ahead again. Further-
more, the algorithm does not prefetch the last read of a
sector because there is the potential that the last sector
read will be the last read of the overall “read operation”. On
the last read, the status will change to indicate the opera-
tion is complete. By not prefetching the last sector read, the
86
SSMI and EXCEP Support in GLIU
Read/Write Response Packets
Subtractive Decoding
Byte Enable Checking in I/O Address
Decoding
IDE Data Port Read Prefetch
31506B
data and status never get out of sync with each other. In
PIDE prefetch mode, hardware always makes four byte
reads to the IDE data register (1F0h) and supplies the four
bytes of read data to IDE read operations ignoring byte
enables of the IDE read operation.
5.2.11
The PPIDE (Post Primary IDE) in GLPCI_MSR_CTRL
(MSR 51000010h[17]) controls post/write on confirmation
for I/O writes of address 1F0h (part of primary IDE
address). If bit 17 is set, a write is completed immediately
on the PCI bus as soon as it is accepted by the GLPCI_SB.
If bit 17 is cleared, an I/O write is completed only after com-
pleting the write in the primary IDE space. Default behavior
is write on confirmation.
5.2.12
For each GLPCI_SB Region Configuration register (0
through 15), if the SPACE bit (bit 32) is programmed for I/O
and bit 3 (PF, Prefetchable) is high, post all I/O writes to
this region. (See Section 6.2.2.2 "Region 0-15 Configura-
tion MSRs (GLPCI_R[x])" on page 238 for further details.)
Use of this feature is most appropriate for GPIO “bit bang-
ing” in the Diverse Device module. Posting writes on the
North Bridge side will not increase performance.
5.2.13
Normally memory writes are posted independent of region
and independent of decode and legacy/non-legacy
address. The USB registers are in memory space and can
not be moved to I/O space due to driver compatibility
issues. In a Geode GX processor/companion device sys-
tem, a memory write is posted and a possibility exists that
a subsequent I/O write will complete before the posted
memory write completes. In order to prevent out of order
execution, when a memory write is issued to the GLIU in
the Geode CS5535 companion device, the request packet
is issued with the send response bit set to serialize the
request. I/O writes are not an issue, since the requests
packet always has the send response bit set.
AMD Geode™ CS5535 Companion Device Data Book
IDE Data Port Write Posting
Other Typical Slave Write Posting
Memory Writes with Send Response
GeodeLink™ PCI South Bridge