CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 258

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.3.2.7
Bus Master 0 Command (ACC_BM0_CMD)
ACC I/O Offset
Type
Reset Value
Bus Master 1 Command (ACC_BM1_CMD)
ACC I/O Offset
Type
Reset Value
Bus Master 2 Command (ACC_BM2_CMD)
ACC I/O Offset
Type
Reset Value
Bus Master 3 Command (ACC_BM3_CMD)
ACC I/O Offset
Type
Reset Value
258
Bit
7:4
1:0
3
2
7
Audio Bus Master 0-7 Command Registers (ACC_BM[x]_CMD)
Name
RSVD
RW (RO)
BYTE_ORD
BM_CTL
20h
R/W
00h
28h
R/W
08h
30h
R/W
00h
38h
R/W
08h
6
31506B
RSVD
Description
Reserved. Reads return 0
Read or Write (Read Only). Indicates the transfer direction of the audio bus master.
This bit always reads 0 for BM [0,2,4,6,7].
This bit always reads 1 for BM[1,3,5].
0: Memory to codec.
1: Codec to memory.
Byte-Order. Sets the byte order for 16-bit samples that this bus master uses.
0: Little Endian (Intel) byte-order (LSBs at lower address).
1: Big Endian (Motorola) byte-order (MSBs at lower address).
Bus Master Pause/Enable Control. Enables, disables, or pauses the bus master.
00: Disable bus master.
01: Enable bus master.
10: Reserved.
11: Pause bus master (if currently enabled) or do nothing (if currently disabled).
When the bus master is enabled by writing 01, the bus master starts up by using the
address in its associated PRD Table Address Register. Writing 00 while the bus master
is enabled causes the bus master to stop immediately. Upon resuming the bus master
uses the address in its PRD Table Address Register. The PRD Table Address Register
must be re-initialized by software before enabling the bus master, or there is a risk that
the bus master may overstep the bounds of the PRD Table.
Note:
5
ACC_BM[x]_CMD Bit Descriptions
When the bus master reaches a PRD with the EOT bit set, these bits are set to
00.
ACC_BM[x]_CMD Register Map
4
Bus Master 4 Command (ACC_BM4_CMD)
ACC I/O Offset
Type
Reset Value
Bus Master 5 Command (ACC_BM5_CMD)
ACC I/O Offset
Type
Reset Value
Bus Master 6 Command (ACC_BM6_CMD)
ACC I/O Offset
Type
Reset Value
Bus Master 7 Command (ACC_BM7_CMD)
ACC I/O Offset
Type
Reset Value
RW
3
AMD Geode™ CS5535 Companion Device Data Book
AC97 Audio Codec Controller Register Descriptions
BYTE_ORD
40h
R/W
00h
48h
R/W
08h
50h
R/W
00h
58h
R/W
00h
2
1
BM_CTL
0