CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 154

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.13.4
The Firmware Hub (FWH) relies on the Intel Firmware Hub
interface to communicate with the outside world. This inter-
face consists of four bidirectional signals and one “control”
input. The timing and the electrical parameters of the FWH
interface are similar to those of the LPC interface. The Intel
FWH interface is designed to use an LPC-compatible Start
cycle, with a reserved cycle type code. This ensures that all
LPC devices present on the shared interface will ignore
cycles destined for the FWH, without becoming “confused”
by the different protocols.
When the FWH interface is active, information is trans-
ferred to and from the FWH by a series of “fields” where
each field contains four bits of data. Many fields are one
clock cycle in length but can be of variable length, depend-
ing upon the nature of the field. Field sequences and con-
tents are strictly defined for read and write operations.
5.13.4.1 FWH Cycles
A cycle is started on the rising edge of LCLK when
LFRAME# is asserted and a valid cycle type is driven on
LAD[3:0] by the host. Valid cycle types for the FWH are
1101b (read) and 1110b (write).
FWH Read Cycles: A read cycle is initiated by asserting
1101b on LAD[3:0] with LFRAME# low. All data transfers
are valid on the rising edge of the LCLK. The cycle is illus-
trated in Figure 5-45 and described in Table 5-27.
154
Number of Clock Cycles
Firmware Hub Interface
(FWH3-FWH0)
LFRAME
LAD[3:0]
(FWH4)
31506B
LCLK
START
1
Figure 5-45. FWH Read Cycle
IDSEL
1
ADDR MSIZE
7
FWH Write Cycles: A write cycle is initiated by asserting
1110b on LAD[3:0] with LFRAME# low. All data transfers
are valid on the rising edge of the LCLK. The cycle is illus-
trated in Figure 5-46 and described in Table 5-28.
Abort Operation: LFRAME# (FWH4) active (low) indi-
cates either that a Start cycle will eventually occur or that
an abort is in progress. In either case, if LFRAME# (FWH4)
is asserted, the Intel FWH will “immediately” TRI-STATE its
outputs and the FWH state machine will reset.
During a write cycle, there is a possibility that an internal
Flash write or erase operation is in progress (or has just
been initiated). If LFRAME# (FWH4) is asserted during this
frame, the internal operation will not abort. The software
must send an explicit Flash command to terminate or Sus-
pend the operation.
The internal FWH state machine will not initiate a Flash
write or erase operation until it has received the last data
nibble from the chip set. This means that LFRAME (FWH4)
can be asserted as late as this cycle (“cycle 12") and no
internal Flash operation will be attempted. However, since
the Intel FWH will start “processing” incoming data before it
generates its SYNC field, it should be considered a non-
buffered peripheral device.
1
AMD Geode™ CS5535 Companion Device Data Book
TAR
2
SYNC
3
DATA
2
TAR
2
Low Pin Count Port