CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 266

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.4.1.4
MSR Address
Type
Reset Value
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns
the value; writing 1 clears the FLAG; writing 0 has no effect.
266
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:37
Bit
36
35
34
33
GLD Error MSR (ATAC_GLD_MSR_ERROR)
Name
RSVD
IDE_PIO_ERR_
FLAG
RESP_EXCEP_
ERR_FLAG
SSMI_ERR_FLAG
BLOCKIO_SSMI_
FLAG
51300003h
R/W
00000000_00000100h
31506B
Description
Reserved. Write as read.
IDE PIO Error. If high, records that an ERR was generated due to a PIO access during
a DMA command. Write 1 to clear; writing 0 has no effect. IDE_PIO_ERR_EN (bit 4)
must be high to generate ERR and set flag.
If IDE_PIO_ERR_EN = 1 and IDE_PIO_ASMI_EN (MSR 51300002h[0]) = 0 and the
error occurs, this bit gets set, and the GLCP master error signal is asserted.
If both IDE_PIO_ERR_EN = 1 and IDE_PIO_ASMI_EN = 1 and the error occurs, this
bit gets set, the GLCP master error signal is asserted, and an SSMI is generated.
Response Exception Error Flag. If high, records that an ERR was generated and the
GLCP master error signal was asserted due to the EXCEP bit being set in the response
packet. Write 1 to clear; writing 0 has no effect. RESP_EXCEP_ERR_EN (bit 3) must
be high to enable these events.
SSMI Error Flag. If high, records that an ERR was generated due to an uncleared
SSMI. Write 1 to clear; writing 0 has no effect. SSMI_ERR_EN (bit 2) must be high to
generate ERR and set flag.
If SSMI_ERR_EN and IDE_PIO_SSMI_FLAG (MSR 51300002h[32]) = 1 and the error
occurs, this bit gets set, the GLCP master error signal is asserted, lb_slav_rdy is
asserted, and an SSMI is generated.
SSMI on I/O write during DMA. If high, records that an I/O write during DMA had
occurred. Write 1 to clear; writing 0 has no effect. BLOCKIO_SSMI_EN (bit 1) and
BLOCKIO (bit 8) must be high to set flag.
ATAC_GLD_MSR_ERROR Bit Descriptions
ATAC_GLD_MSR_ERROR Register Map
RSVD
RSVD
AMD Geode™ CS5535 Companion Device Data Book
ATA-5 Controller Register Descriptions
9
8
7
RSVD
6
5
4
3
2
1
0