CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 531

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.20
The GeodeLink Control Processor’s (GLPC) register set
consists of:
• Standard GeodeLink Device (GLD) MSRs
• GLCP Specific MSRs
The MSRs (both Standard and GLPC Specific) are
accessed via the RDMSR and WRMSR processor instruc-
AMD Geode™ CS5535 Companion Device Data Book
51700018h-
5170000Ch
5170000Dh
51700000h
51700001h
51700002h
51700003h
51700004h
51700005h
51700008h
51700009h
5170000Ah
5170000Bh
5170000Eh
5170000Fh
51700010h
51700011h
51700012h
51700013h
51700014h
51700015h
51700016h
51700017h
517000FFh
Address
Address
MSR
MSR
GeodeLink™ Control Processor Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Table 6-71. Standard GeodeLink™ Device MSRs Summary
Register
GLD Capabilities MSR (GLCP_GLD_MSR_CAP)
GLD Master Configuration MSR
(GLCP_GLD_MSR_CONFIG)
GLD SMI MSR (GLCP_GLD_MSR_SMI)
GLD Error MSR (GLCP_GLD_MSR_ERROR)
GLD Power Management MSR
(GLCP_GLD_MSR_PM)
GLD Diagnostic MSR (GLCP_GLD_MSR_DIAG)
Register
GLCP Clock Disable Delay Value
(GLCP_CLK_DIS_DELAY)
GLCP Clock Mask for Sleep Request
(GLCP_PMCLKDISABLE)
GLCP Fabrication (GLCP_FAB)
GLCP Global Power Management Control
(GLCP_GLB_PM)
GLCP Debug Output from Chip (GLCP_DBGOUT)
Reserved Registers (GLPC_RSVD)
Software Communication Register
(GLCP_DOWSER)
GLCP Reserved Register (GLPC_RSVD)
GLCP Clock Control (GLCP_CLKOFF)
GLCP Clock Active (GLCP_CLKACTIVE)
GLCP Clock Mask for Debug Clock Stop Action
(GLCP_CLKDISABLE)
GLCP Clock Active Mask for Suspend Acknowledge
(GLCP_CLK4ACK)
GLCP System Reset Control (GLCP_SYS_RST)
Reserved Registers (GLPC_RSVD)
GLCP Debug Clock Control (GLCP_DBGCLKCTL)
Chip Revision ID (GLCP_CHIP_REV_ID)
Reserved Registers (GLPC_RSVD) - Reserved for
internal testing. Do not write to these registers.
Table 6-72. GLPC Specific MSRs Summary
tions. The MSR address is derived from the perspective of
the CPU Core. See Section 4.2 "MSR Addressing" on page
59 for more details.
The tables that follow are register summary tables that
include reset values and page references where the bit
descriptions are provided.
00000000_00000003h
00000000_00000000h
00000000_00000000h
00000000_00000002h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000002h
00000000_002021xxh
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
0000000x_xxxxxxxxxh
00000000_00000000h
00000000_00000000h
00000000_000000xxh
xxxxxxxx_xxxxxxxxh
Reset Value
Reset Value
31506B
Reference
Reference
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