MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 102

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.13.4.2.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1),
the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated
PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source.
On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an
edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled
(PWMEx = 0), the counter for the channel does not count.
4.13.4.2.2
Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram
as a mux select of either the Q output or the Q output of the PWM output flip flop. When one of the bits in the PWMPOL register
is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is
reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.
Freescale Semiconductor
D2D Clock
PWMEx
(Clock Edge
Sync)
Gate
PWM Enable
The first PWM cycle after enabling the channel can be irregular.
PWM Polarity
Up/Down
8-Bit Counter
PWMCNTx
Q
Q
Figure 26. PWM Timer Channel Block Diagram
Reset
T
R
NOTE
8-bit Compare =
8-bit Compare =
PWMPERx
PWMDTYx
CAEx
T
R
PWM Control Module (PWM8B2C)
Q
Q
PPOLx
M
U
X
MM912F634
PWM
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