MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 236

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.4.4.1
On entering Final State, a trigger may be issued to the trace buffer according to the trace alignment control, as defined by the
TALIGN bit (see
the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case, or upon
completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to
the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor
breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed.
4.31.4.5
The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a
circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide
word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next
read will receive fresh information. Data is stored in the format shown in
DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer, whilst the DBG
is armed, returns invalid data and the trace buffer pointer is not incremented.
4.31.4.5.1
Using the TALIGN bit (see
the end or the beginning of a tracing session.
If End tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State
signals the end of the tracing session. Tracing with Begin Trigger starts at the opcode of the trigger. Using End Trigger, or when
the tracing is initiated by writing to the TRIG bit whilst configured for Begin-Trigger, tracing starts at the second opcode after
writing to DBGC1
4.31.4.5.1.1
Storing with Begin Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met
the DBG module will remain armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow
instruction, the change of flow associated with the trigger will be stored in the Trace Buffer. Using Begin Trigger together with
tagging, if the tagged instruction is about to be executed, then the trace is started. Upon completion of the tracing session, the
breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.
4.31.4.5.1.2
Storing with End Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module will
become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event
will not be stored in the Trace Buffer.
4.31.4.5.2
Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using
the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections. The trace buffer organization
is shown in
Freescale Semiconductor
Table
Trace Buffer Operation
Section 4.31.3.2.3, “Debug Trace Control Register
312.
Final State
Trace Trigger Alignment
Storing with Begin Trigger
Storing with End Trigger
Trace Modes
Section 4.31.3.2.3, “Debug Trace Control Register
(DBGTCR)"”). If the TSOURCE bit in DBGTCR is clear then
Table
(DBGTCR)"”) it is possible to align the trigger with
312. After each store, the counter register
S12S Debug (S12SDBGV1) Module
MM912F634
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