MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 190

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.29
4.29.1
The 9S12I32PIMV1 module decodes the priority of all system exception requests and provides the applicable vector for
processing the exception to the CPU. The 9S12I32PIMV1 module supports:
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
4.29.1.1
4.29.1.2
4.29.1.3
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I bit and X bit maskable interrupt requests
A non-maskable unimplemented opcode trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector
CCR — Condition Code Register (in the CPU)
ISR — Interrupt Service Routine
MCU — Micro-controller Unit
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base + 0x0080). The vector base is a 16-bit address which is
accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower
byte).
2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
I bit maskable interrupts can be nested.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base
+ 0x00F6).
One non-maskable unimplemented opcode trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU request
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.
Run mode
This is the basic mode of operation.
Wait mode
In wait mode, the clock to the 9S12I32PIMV1 module is disabled. The 9S12I32PIMV1 module is however capable of
waking up the CPU from wait mode if an interrupt occurs. Please refer to
Mode"”
Stop mode
In stop mode, the clock to the 9S12I32PIMV1 module is disabled. The 9S12I32PIMV1 module is however capable of
waking up the CPU from stop mode if an interrupt occurs. Please refer to
Mode"”
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to
Section 4.29.3.1.1, “Interrupt Vector Base Register (IVBR)"”
Interrupt Module (S12SINTV1)
Introduction
Glossary
Features
Modes of Operation
for details.
for details.
for details.
Section 4.29.5.3, “Wake-up from Stop or Wait
Section 4.29.5.3, “Wake-up from Stop or Wait
Interrupt Module (S12SINTV1)
MM912F634
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