MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 227

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 292. DBGXCTL Field Descriptions (continued)
Table 293
is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue.
4.31.3.2.8.2
Table 294. Debug Comparator Address High Register (DBGXAH)
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F.
Freescale Semiconductor
Address: 0x0029
Reset
W
R
COMPE
Field
RWE
BRK
TAG
RW
5
4
3
2
0
shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit
0
0
7
Table 293. Read or Write Comparison Logic Table
Debug Comparator Address High Register (DBGXAH)
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer
transition or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the
instruction queue.
0 Allow state sequencer transition immediately on match
1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
Break— This bit controls whether a comparator match terminates a debug session immediately, independent of state
sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit
DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active,
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated
comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set.
0 Write cycle will be matched
1 Read cycle will be matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated
comparator.This bit is ignored if the TAG bit in the same register is set
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
is terminated and the module disarmed.
RWE Bit
0
0
1
1
1
1
0
0
6
RW Bit
Table 295. Comparator Address Register Visibility
0
0
1
1
x
x
COMRV
00
5
0
0
RW Signal
0
1
0
1
0
1
DBGAAH, DBGAAM, DBGAAL
0
0
4
Visible Comparator
Description
RW not used in comparison
RW not used in comparison
0
0
3
Read data bus
Write data bus
Comment
No match
No match
S12S Debug (S12SDBGV1) Module
0
0
2
Bit 17
1
0
MM912F634
Bit 16
0
0
227