MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 200

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.30.3.2.3
Table 254. BDM Program Page Register (BDMPPR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
Table 255. BDMPPR Field Descriptions
4.30.3.3
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x3_FF0F). The read-only value is a unique family
ID which is 0xC2 for devices with HCS12S core.
4.30.4
The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands:
hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active background debug mode,
see
Firmware commands are used to read and write CPU resources and to exit from active background debug mode, see
Section 4.30.4.4, “Standard BDM Firmware
register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see
Section 4.30.4.3, “BDM Hardware
can only be executed when the system is not secure and is in active background debug mode (BDM).
Freescale Semiconductor
BPP[3:0]
Address 0x3_FF08
Section 4.30.4.3, “BDM Hardware
BPAE
Field
3–0
Register Global
7
Reset
W
R
Functional Description
BDM Program Page Access Enable Bit — BPAE enables program page access for BDM hardware and firmware read/write
instructions. The BDM hardware commands used to access the BDM registers (READ_BD and WRITE_BD), and can not be
used for global accesses even if the BGAE bit is set.
0 BDM Program Paging disabled
1 BDM Program Paging enabled
BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed information regarding
the program page window scheme, refer to the S12S_MMC Block Guide.
Family ID Assignment
BDM Program Page Index Register (BDMPPR)
BPAE
7
0
Commands"”), and in secure mode (see
Commands"”. Target system memory includes all memory that is accessible by the CPU.
6
0
0
Commands"”. The CPU resources referred to are the accumulator (D), X index
5
0
0
Description
4
0
0
Section 4.30.4.1,
BPP3
3
0
Background Debug Module (S12SBDMV1)
BPP2
“Security"”). Firmware commands
2
0
BPP1
1
0
MM912F634
BPP0
0
0
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