MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 176

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.28
4.28.1
This section describes the functionality of the module mapping control (MMC) sub-block of the S12S platform. The block diagram
of the MMC is shown in
The MMC module controls the multi-master priority accesses (BDM and CPU), the selection of internal resources. Internal buses,
including internal memories and peripherals, are controlled in this module. The local address space for each master is translated
to a global memory space using the PPAGE register.
4.28.1.1
4.28.1.2
The main features of this block are:
Freescale Semiconductor
Table 238. Acronyms and Abbreviations
•
•
•
•
•
•
Unimplemented areas
Paging capability to support a global 256 Kilobytes memory address space
Bus arbitration between the masters CPU, BDM to different resources (internal and peripherals). Note: resources are
also called targets.
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong
to any of the on-chip modules) in single-chip modes
Mis-aligned address
single-chip modes
Aligned address
global address
normal modes
special modes
Memory Mapping Control (S12SMMCV1)
Logic level “1”
Logic level “0”
local address
Bus Clock
Introduction
word
MCU
NVM
byte
Terminology
Features
IFR
NS
SS
0x
x
Figure
47.
Voltage that corresponds to Boolean true state
Voltage that corresponds to Boolean false state
Represents hexadecimal number
Represents logic level ’don’t care’
8-bit data
16-bit data
based on the 64 Kilobytes Memory Space (16-bit address)
based on the 256 Kilobytes Memory Space (18-bit address)
Address on even boundary
Address on odd boundary
System Clock. Refer to CRG Block Guide.
Normal Single-chip mode
Special Single-chip mode
Normal Single-chip mode
Special Single-chip mode
Normal Single-chip mode
Special Single-chip mode
Areas which are accessible by the PPAGE, and not implemented
Micro-Controller Unit
Non-volatile Memory; Flash EEPROM or ROM
NVM Information Row. Refer to FTSR Block Guide
Memory Mapping Control (S12SMMCV1)
MM912F634
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