MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 315

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.38.3.2.1
Table 401. SPI Control Register 1 (SPICR1)
Read: Anytime
Write: Anytime
Table 402. SPICR1 Field Descriptions
Freescale Semiconductor
0x00E8
Reset
W
R
LSBFE
SPTIE
MSTR
CPHA
SSOE
CPOL
Field
SPIE
SPE
7
6
5
4
3
2
1
0
SPIE
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if the SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is
cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if the SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI
from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the
SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock.
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the
SSOE as shown in
system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data
register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the
SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
0
7
SPI Control Register 1 (SPICR1)
SPE
0
6
Table
403. In master mode, a change of this bit will abort a transmission in progress and force the SPI
SPTIE
5
0
MSTR
0
4
Description
CPOL
0
3
Serial Peripheral Interface (S12SPIV4)
CPHA
1
2
SSOE
1
0
MM912F634
LSBFE
0
0
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