MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 322

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading
data from the read data buffer and for writing data to the transmit data register.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of
four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The
CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on
even numbered SCK edges (see
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode
is selected, when the MSTR bit is clear, slave mode is selected.
4.38.4.1
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission
begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register.
The byte begins shifting out on the MOSI pin under the control of the serial clock.
Freescale Semiconductor
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Serial clock
The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate
preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the
transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls
the shift register of the slave peripheral.
MOSI, MISO pin
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by
the SPC0 and BIDIROE control bits.
SS pin
If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each
transmission and is high when the SPI is in idle state.
If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input
becomes low, this indicates a mode fault error, where another master tries to drive the MOSI and SCK lines. In this case,
the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO
(or SISO in bidirectional mode). The result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a
transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable
bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested.
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started
within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI
clock phase bit, CPHA, in SPI control register 1 (see
Master Mode
A change of CPOL or MSTR bit while there is a received byte pending in the receive shift
register will destroy the received byte and must be avoided.
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with
SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in
progress and force the SPI into idle state. The remote slave cannot detect this, therefore the
master must ensure that the remote slave is returned to idle state.
Section 4.38.4.3, “Transmission
NOTE
NOTE
Section 4.38.4.3, “Transmission
Formats"”).
Serial Peripheral Interface (S12SPIV4)
Formats"”).
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