MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 154

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 202. MM912F634 Analog Die Trimming Registers
Note:
Functional Description and Application Information
4.25
A trimming option is implemented to increase some device parameter accuracy. As the MM912F634 analog die is exclusively
combined with a FLASH- MCU, the required trimming values can be calculated during the final test of the device, and stored to
a fixed position in the FLASH memory. During start-up of the system, the trimming values have to be copied into the MM912F634
analog die trimming registers.
The trimming registers will maintain their content during Low Power mode, Reset will set the default value.
4.25.1
4.25.1.1
There are four trimming registers implemented (CTR0…CTR3), with CTR2 being reserved for future use. The following table
shows the registers used.
At system startup, the trimming information have to be copied from the MCU IFR Flash location to the corresponding MM912F634
analog die trimming registers. The following table shows the register correlation.
Freescale Semiconductor
Offset
142.
0xF0
0xF1
0xF2
0xF3
(142)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 203. MM912F634 - MCU vs. Analog Die Trimming Register Correlation
Note:
143.
MM912F634 - Analog Die Trimming
Trimming Reg 0
Trimming Reg 1
Trimming Reg 2
Trimming Reg 3
Memory Map and Register Definition
Module Memory Map
Name
CTR0
CTR1
CTR2
CTR3
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Two word (16-Bit) transfers including CTR2 are recommended at system startup. The IFR
register has to be enabled for reading
(MMCCTL1)")
To trim the bg1p25sleep there is two steps:
Step 1: First choose the right trim step by adjusting SLPBGTR[2:0] with SLPBGTRE=1,
SLPBG_LOCK bit has to stay at 0.
Step 2: Once the trim value is known, correct SLPBGTR[2:0], SLPBGTRE and
SLPBG_LOCK bits have to be set at the same time to apply and lock the trim. Once the trim
is locked, no other trim on the parameter is possible.
Name
CTR0
CTR1
CTR2
CTR3
W
W
W
W
R
R
R
R
OFFCTRE
LINTRE
BGTRE
7
0
OFFCTR2
CTR1_6
LINTR
MCU IFR Address
6
0
0x4C
0x4D
0x4E
0x4F
BGTRIMUP
OFFCTR1
WDCTRE
(Section 4.28.2.2.4, “MMC Control Register
5
0
NOTE
BGTRIMDN
SLPBGTRE
OFFCTR0
CTR0_4
4
SLPBG_LOCK
IREFTRE
CTR3_E
CTR0_3
3
Analog Offset
MM912F634 - Analog Die Trimming
SLPBGTR2
WDCTR2
IREFTR2
0xF0
0xF1
0xF2
0xF3
CTR3_2
2
(143)
SLPBGTR1
WDCTR1
IREFTR1
CTR3_1
1
MM912F634
SLPBGTR0
WDCTR0
IREFTR0
CTR3_0
0
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