MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 254

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.32.5.2
The reset sequence is initiated by any of the following events:
Upon detection of any reset event, an internal circuit drives the RESET pin low for 516 DCO Clock cycles. Depending on internal
synchronization latency, it can also be 517 DCO Clock cycles (see
require a running DCO Clock. However, the internal reset circuit of the 9S12I32PIMV1 cannot sequence out of current reset
condition without a running DCO Clock. After 516 DCO Clock cycles, the RESET pin is released. The reset generator of the
9S12I32PIMV1 waits for additional 256 DCO Clock cycles and then samples the RESET pin to determine the originating source.
Table 334
The internal reset of the MCU remains asserted while the reset generator completes the 768 DCO Clock long reset sequence.
In case the RESET pin is externally driven low for more than these 768 DCO Clock cycles (External Reset), the internal reset
remains asserted longer.
4.32.5.2.1
In case of loss of clock, or the oscillator frequency is below the failure assert frequency f
for values), the 9S12I32PIMV1 generates a Oscillator Monitor Reset.
Freescale Semiconductor
Table 334. Reset Vector Selection
(256 cycles after release)
•
•
•
•
•
Sampled RESET Pin
Low level is detected at the RESET pin (External Reset).
Power-on is detected.
Illegal Address Access is detected (see MMC Block Guide for details).
COP watchdog times out.
Oscillator monitor failure is detected.
shows which vector will be fetched.
1
1
1
0
Description of Reset Operation
External circuitry connected to the RESET pin should not include a large capacitance that
would interfere with the ability of this signal to rise to a valid logic one within 256 DCO Clock
cycles after the low drive is released.
Oscillator Monitor Reset
DCO Clock
RESET
Oscillator monitor
fail pending
0
1
0
X
possibly DCO Clock n
ot running
S12SCRG drives RESET pin low
Figure 77. RESET Timing
) (
COP timeout
pending
516 cycles
NOTE
X
X
0
1
) (
)
Figure
(
77). Since entry into reset is asynchronous, it does not
S12S Clocks and Reset Generator (S12SCRGV1)
POR /Illegal Address Access/ External pin RESET
POR /Illegal Address Access/External pin RESET
RESET pin
released
256 cycles
)
OMFA
(
possibly RESET driv-
en low externally
Oscillator Monitor Fail
(see device electrical characteristics
Vector Fetch
COP time out
)
(
MM912F634
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