MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 221

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents.
Table 273. DBGTB Field Descriptions
4.31.3.2.6
Table 274. Debug Count Register (DBGCNT)
Read: Anytime
Write: Never
Table 275. DBGCNT Field Descriptions
Freescale Semiconductor
Address: 0x0026
Reset
POR
CNT[5:0]
Bit[15:0]
W
R
Field
Field
15–0
TBF
5–0
7
Table 276. CNT Decoding Table
Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the Trace Buffer
may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next
address to be read. When the ARM bit is written to 1, the trace buffer is locked to prevent reading. The trace buffer can only be
unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can
be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the
trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed
and for reads with the TSOURCE bit clear. The POR state is undefined. Other resets do not affect the trace buffer contents.
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If
this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in
DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no
affect on this bit.
This bit is also visible at DBGSR[7]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer.
the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero,
the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger mode. The DBGCNT register is cleared when
ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization, but is not cleared by other
system resets. Thus, should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the
number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading
from the trace buffer.
TBF
—
0
7
TBF
Debug Count Register (DBGCNT)
0
0
1
—
0
0
6
CNT[5:0]
000000
000001
000010
000100
000000
000110
111111
…
—
5
0
ARM bit will be cleared and the tracing session ends.
—
0
4
64 lines valid; if using Begin trigger alignment,
Description
Description
—
0
3
No data valid
63 lines valid
Description
2 lines valid
4 lines valid
6 lines valid
1 line valid
…
CNT
—
S12S Debug (S12SDBGV1) Module
0
2
—
1
0
Table 276
MM912F634
—
0
0
shows
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