MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 273

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 350. S12SFTSR32K Register Summary (Normal/Special Mode) (continued)
Functional Description and Application Information
4.36.3.3.1
The FCLKDIV register is used to control the length of timed events in program and erase algorithms executed by the Flash
memory controller.
Table 351. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable and writable with restrictions, as determined by the value of FDIVLD when writing
to the FCLKDIV register (see
Table 352. FCLKDIV Field Descriptions
Freescale Semiconductor
0x0100
Reset
FADDRLO
FDATALO
FDIVLD
FADDRHI
FDATAHI
W
Register
R
0x010C
0x010D
0x0107
0x0108
0x0109
0x010A
0x010B
0x010E
0x010F
Field
FRSV1
FRSV2
FRSV3
FRSV4
FRSV5
Name
7
FDIVLD
Clock Divider Load Control — When writing to the FCLKDIV register for the first time after a reset, the value of the FDIVLD
bit written controls the future ability to write to the FCLKDIV register:
0 Writing a 0 to FDIVLD locks the FCLKDIV register contents; all future writes to FCLKDIV are ignored.
1 Writing a 1 to FDIVLD keeps the FCLKDIV register writable; next write to FCLKDIV is allowed.
When reading the FCLKDIV register, the value of the FDIVLD bit read indicates the following:
0 FCLKDIV register has not been written to since the last reset.
1 FCLKDIV register has been written to since the last reset.
0
7
W
W
W
W
W
W
W
W
W
Flash Clock Divider Register (FCLKDIV)
R
R
R
R
R
R
R
R
R
FAB7
FD15
Bit 7
FD7
0
0
0
0
0
0
0
PRDIV8
Table
0
6
352).
FAB6
FD14
FD6
6
0
0
0
0
0
0
0
5
0
FAB13
FAB5
FD13
FD5
5
0
0
0
0
0
0
0
0
4
FAB12
FAB4
FD12
Description
FD4
4
0
0
0
0
0
0
0
0
3
FAB11
FAB3
FD11
FDIV[5:0]
FD3
3
0
0
0
0
0
0
0
32 kbyte Flash Module (S12SFTSR32KV1)
0
2
FAB10
FAB2
FD10
FD2
2
0
0
0
0
0
0
0
1
0
FAB9
FAB1
FD9
FD1
1
0
0
0
0
0
0
0
MM912F634
FAB8
FAB0
Bit 0
0
FD8
FD0
0
0
0
0
0
0
0
0
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