MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 325

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Figure 103
diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly
between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the
master. The SS pin of the master must be either high or reconfigured as a general purpose output not affecting the SPI.
In slave mode, if the SS line is not de-asserted between the successive transmissions, then the content of the SPI data register
is not transmitted. Instead, the last received byte is transmitted. If the SS line is de-asserted for at least minimum idle time (half
SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted.
In master mode, with slave select output enabled the SS line is always de-asserted and reasserted between successive transfers
for at least minimum idle time.
Freescale Semiconductor
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
t
t
t
t
MOSI pin
MISO pin
MSB first (LSBFE = 0):
L
T
I
L
LSB first (LSBFE = 1):
, t
= Minimum idling time between transfers (minimum SS high time)
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The
T
, and t
I
are guaranteed for the master mode and required for the slave mode.
t
L
MSB
LSB
1
2
Begin
Bit 6
Bit 1
Figure 103. SPI Clock Format 0 (CPHA = 0)
3
4
Bit 5
Bit 2
5
6
Bit 4
Bit 3
7
Transfer
8
Bit 3
Bit 4
9
10
Bit 2
Bit 5
11
12
Bit 1
Bit 6
13 14
Serial Peripheral Interface (S12SPIV4)
End
MSB
15
LSB
16
Minimum 1/2 SCK
t
T
for t
Begin of Idle State
T
t
, t
I
l
, t
L
t
L
MM912F634
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