MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 199

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 252. BDMSTS Field Descriptions
Table 253. BDM CCR Holding Register (BDMCCR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR holding register is used to save the condition code register of the user’s
program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written
to modify the CCR value.
Freescale Semiconductor
Special Single-chip Mode
BDMACT
ENBDM
UNSEC
TRACE
Field
SDV
Register Global Address
All Other Modes
7
6
4
3
1
Reset
W
R
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow
firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still
allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware out of reset in special single chip mode. In special single-chip mode with the device
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled
and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part
of the exit sequence to return to user code and remove the BDM memory from the map.
0 BDM not active
1 BDM active
Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a
firmware or hardware read command or after data has been received as part of a firmware or hardware write command. It is
cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to
control program flow execution.
0 Data phase of command not complete
1 Data phase of command is complete
TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware command is first
recognized. It will stay set until BDM firmware is exited by one of the following BDM commands: GO or GO_UNTIL
0 TRACE1 command is not being executed
1 TRACE1 command is being executed
Unsecure — If the device is secured this bit is only writable in special single-chip mode from the BDM secure firmware. It is
in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory
map overlapping the standard BDM firmware lookup table.
The secure BDM firmware lookup table verifies that the on-chip Flash is erased. This being the case, the UNSEC bit is set and
the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is
turned off. If the erase test fails, the UNSEC bit will not be asserted.
0 System is in a secured mode.
1 System is in a unsecured mode.
Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM.
0x3_FF06
secured, this bit will not be set by the firmware until after the Flash erase verify tests are complete.
Note that if the user does not change the state of the bits to “unsecured” mode, the system will be secured again when
it is next taken out of reset. After reset this bit has no meaning or effect when the security byte in the Flash EEPROM
is configured for unsecure mode.
CCR7
1
0
7
CCR6
1
0
6
CCR5
0
0
5
Description
CCR4
4
0
0
CCR3
Background Debug Module (S12SBDMV1)
1
0
3
CCR2
0
0
2
CCR1
0
0
1
MM912F634
(166)
CCR0
0
0
0
.
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