MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 212

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Upon detecting the SYNC request from the host, the target performs the following steps:
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM
communications. Typically, the host can determine the correct communication speed within a few percent of the actual target
speed, and the communication protocol can easily tolerate speed errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is
referred to as a soft-reset, equivalent to a timeout in the serial communication. After the SYNC response, the target will consider
the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular
SYNC command. Note that one of the possible causes for a command not to be acknowledged by the target is a host-target
synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse
will not be issued.
4.30.4.10
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single
instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware, and the BDM is
active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed.
This facilitates stepping or tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is
executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt
service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free
running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer
exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address
pointing to BDM firmware address space.
When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction
is traced:
Freescale Semiconductor
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Discards any incomplete command received or bit retrieved.
Waits for BKGD to return to a logic one.
Delays 16 cycles to allow the host to stop driving the high speedup pulse.
Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
Removes all drive to the BKGD pin so it reverts to high-impedance.
The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving the low power mode.
This is the case because BDM active mode can not be entered after CPU executed the stop instruction. However all
BDM hardware commands except the BACKGROUND command are operational after tracing a stop or wait instruction,
and still in stop or wait mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is
operational.
As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of
the corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded
when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the
TRACE1 command after CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait
mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled
only when system stop mode has been reached. Hence after a system stop mode the handshake feature must be
enabled again by sending the ACK_ENABLE command.
Instruction Tracing
Background Debug Module (S12SBDMV1)
MM912F634
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