MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 310

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.37.4.5
4.37.4.5.1
In run mode with the D2D Interface enable (D2DEN) bit in the D2D control register 0 clear, the D2DI system is in a low-power,
disabled state. D2D registers remain accessible, but clocks to the core of this module are disabled. On D2D lines the GPIO
function is activated.
4.37.4.5.2
D2DI operation in wait mode depends upon the state of the D2DSWAI bit in D2D control register 0.
4.37.4.5.3
If the CPU enters the STOP mode, the D2DI shows the same behavior as with the wait mode with an activated D2DSWAI bit.
4.37.4.6
In case of reset, any transaction is immediately stopped and the D2DI module is disabled.
4.37.4.7
The D2DI only originates interrupt requests, when D2DI is enabled (D2DIE bit in D2DCTL0 set). There are two different interrupt
requests from the D2D module. The interrupt vector offset and interrupt priority are chip dependent.
4.37.4.7.1
This is a level sensitive active high external interrupt driven by the D2DINT input. This interrupt is enabled if the D2DIE bit in the
D2DCTL1 register is set. The interrupt must be cleared using an target specific clearing sequence. The status of the D2D input
pin can be observed by reading the D2DIF bit in the D2DSTAT1 register.
The D2DINIT signal is asserted also in the wait and stop mode; it can be used to leave these modes.
4.37.4.7.2
Those D2D interface specific interrupts are level sensitive and are all cleared by writing a 1 to the ERRIF flag in the D2DSTAT0
register. This interrupt is not locally maskable and should be tied to the highest possible interrupt level in the system, on an S12
architecture to the XIRQ. See the chapter “Vectors” of the MCU description for details.
Freescale Semiconductor
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If D2DSWAI is clear, the D2DI operates normally when the CPU is in the wait mode
If D2DSWAI is set and the CPU enters the wait mode, any pending transmission is completed. When the D2DCLK
output is driven low, the clock generation is stopped, all internal clocks to the D2DI module are stopped, and the module
enters a power saving state.
Low Power Mode Options
Reset
Interrupts
D2DI in Run Mode
D2DI in Wait Mode
D2DI in Stop Mode
D2D External Interrupt
D2D Error Interrupt
To read data bus (D2DSTAT1.D2DIF)
D2DINTI
Figure 97. D2D External Interrupt Scheme
D2DIE
D2DINT
Die-to-Die Initiator (D2DIV1)
MM912F634
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