MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 140

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.18.4.3
Clearing the I/O (input/output) select bit, IOSn, configures channel n as an input capture channel. The input capture function
captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the
timer transfers the value in the timer counter into the timer channel registers, TCn.
The minimum pulse width for the input capture input is greater than two bus clocks.
An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests.
4.18.4.4
Setting the I/O select bit, IOSn, configures channel n as an output compare channel. The output compare function can generate
a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel
registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets
the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests.
The output mode and level bits, OMn and OLn, select set, clear, toggle on output compare. Clearing both OMn and OLn
disconnects the pin from the output logic.
Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output compare does not set the
channel flag.
A successful output compare on channel 3 overrides output compares on all other output compare channels. The output compare
3 mask register masks the bits in the output compare 3 data register. The timer counter reset enable bit, TCRE, enables channel
3 output compares to reset the timer counter. A channel 3 output compare can reset the timer counter even if the IOC3 pin is
being used as the pulse accumulator input.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch.
When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
4.18.5
4.18.5.1
The reset state of each individual bit is listed within the Register Description section
details the registers and their bit-fields.
4.18.6
4.18.6.1
This section describes interrupts originated by the TIM16B4C block.
communicate with the MCU.
Freescale Semiconductor
Table 186. TIM16B4C Interrupts
Interrupt
C[3:0]F
TOF
Resets
Interrupts
Input Capture
Output Compare
General
General
Offset
-
-
Vector
-
-
Priority
-
-
Timer Channel 3-0
Timer Overflow
Source
Table 186
lists the interrupts generated by the TIM16B4C to
4.18.3, “Memory Map and
Active high timer channel interrupts 3-0
Basic Timer Module - TIM (TIM16B4C)
Timer Overflow interrupt
Description
Registers“, which
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