MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 235

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.4.3.4
In case of simultaneous matches, the priority is resolved according to
possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described in
that in the case of simultaneous matches, the match on the lower channel number (0,1,2) has priority. The SC[2:0] encoding
ensures that a match leading to final state has priority over all other matches independent of current state sequencer state. When
configured for range mode on Comparators A/B, match0 has priority whilst match2 is suppressed if a simultaneous range and
Comparator C match occur.
Table 311. Channel Priorities
4.31.4.4
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once
the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered.
Further transitions between the states are then controlled by the state control registers and channel matches. The only permitted
transition from Final State is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each
transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state.
Alternatively writing to the TRIG bit in DBGSC1, the Final State is entered and tracing starts immediately if the TSOURCE bit is
configured for tracing.
Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate
breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an
immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If
a debug session is ended by a match on a channel with BRK = 1, the state sequencer transitions through Final State for a clock
cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state
sequencer enters state0 and the debug module is disarmed.
Freescale Semiconductor
Priority
Highest
Lowest
State Sequence Control
Channel Priorities
(Disarmed)
State 0
ARM = 0
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
ARM = 0
Source
TRIG
Session Complete
(Disarm)
ARM = 1
ARM = 0
Figure 71. State Sequencer Diagram
Final State
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Table
State1
311. The lower priority is suppressed. It is thus
Enter Final State
State3
Action
S12S Debug (S12SDBGV1) Module
State2
Table 311
MM912F634
dictate
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