MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 248

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.32.3.2.2
Table 322. 9S12I32PIMV1 Control Register (CRGCTL1)
Read: Anytime
Write: Anytime
Table 323. CRGCTL1 Field Descriptions
4.32.3.2.3
This register determines the multiplication factor to generate the DCO Clock.
Table 324. 9S12I32PIMV1 FLL Multiply Register (CRGMULT)
Read: Anytime
Write: Anytime
Writing the CRGMULT register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register.
Freescale Semiconductor
0x0035
0x0036
Reset
Reset
BDIV[3:0]
7, 6, 5, 4
LOCKIE
W
W
R
R
Field
1
Bus Divider Bits
Depending on the setting of the BCLKS bit, either the DCO Clock or the Oscillator Clock is divided down in frequency to create
the Core Clock. Bus frequency is Core frequency divided by 2.
0000 divide by 1
0001 divide by 2
0010 divide by 3
0011 divide by 4
0100 divide by 5
0101 divide by 6
0110 divide by 7
0111 divide by 8
1000 divide by 9
1001 divide by 10
1010 divide by 11
1011 divide by 12
1100 divide by 13
1101 divide by 14
1110 divide by 15
1111 divide by 16
FLL Lock Interrupt Enable Bit
0 FLL Lock Interrupt requests are disabled.
1 FLL Lock Interrupt will be requested whenever LOCKIF is set.
0
0
0
7
7
9S12I32PIMV1 Control Register 1 (CRGCTL1)
9S12I32PIMV1 FLL Multiply Register (CRGMULT)
0
0
6
6
BDIV[3:0]
5
0
5
0
0
0
4
4
Description
MULT[6:0]
S12S Clocks and Reset Generator (S12SCRGV1)
0
0
0
3
3
0
0
0
2
2
LOCKIE
1
0
1
0
MM912F634
0
0
0
0
0
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