MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 247

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.32.3.2.1
Table 320. 9S12I32PIMV1 Control Register 0 (CRGCTL0)
Read: Anytime
Write: See individual bit descriptions.
Writing the CRGCTL0 register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register.
Table 321. CRGCTL0 Field Descriptions
Freescale Semiconductor
0x0034
OSC4MHZ
Reset
RDIV[2:0]
OSCEN
BCLKS
W
R
6, 5, 4
REFS
Field
7
3
2
1
OSCEN
Oscillator Enable Bit
0 Oscillator Clock and Oscillator Monitor are disabled.
1 Oscillator Clock and Oscillator Monitor are enabled.
Reference Divider Bits
These bits divide the Oscillator Clock down in frequency.
Divided down frequency must be in the allowed range for f
000 divide by 128
001 divide by 160
010 divide by 192
011 divide by 256
100 divide by 320
101 divide by 384
110 divide by 512
111 Reserved
Bus Clock Source Select Bit
Writing BCLKS = 1 is only possible if oscillator startup flag is set (UPOSC = 1).
BCLKS is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop Mode.
0 DCO Clock is selected as basis for the Bus Clock.
1 Oscillator Clock is selected as basis for the Bus Clock. DCO is disabled.
Reference Select Bit
Writing REFS = 1 is only possible if oscillator startup flag is set (UPOSC = 1).
REFS is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop Mode.
0 Internal Reference Clock is selected as FLL Reference Clock.
1 Divided down Oscillator Clock is selected as FLL Reference Clock.
4.0 MHz Oscillator low pass filter select Bit
The Oscillator contains a noise filter in its signal path from EXTAL/XTAL to chip internal Oscillator Clock. This is to improve high
frequency noise immunity. Writing OSC4MHZ is only possible if OSCEN was zero before.
0 Oscillator uses noise filter with high bandwidth. To be used with crystals/resonators > 4.0 Mhz.
1 Oscillator uses noise filter with low bandwidth. To be used with crystals/resonators = 4.0 Mhz. Choosing a low bandwidth in
0
7
case of a 4.0 MHz crystal/resonator further improves noise immunity at lower frequencies.
9S12I32PIMV1 Control Register 0 (CRGCTL0)
0
6
RDIV[2:0]
5
0
0
4
Description
FLLREF
BCLKS
. See device electrical characteristics for details.
S12S Clocks and Reset Generator (S12SCRGV1)
0
3
REFS
0
2
OSC4MHZ
1
0
MM912F634
0
0
0
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