MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 169

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 219. PIM Reserved Register
Table 220. Port A Data Direction Register (DDRA)
Table 222. PIM Reserved Register
Note:
Note:
Note:
Table 221. DDRA Register Field Descriptions
Functional Description and Application Information
4.27.3.2
155.
4.27.3.3
156.
4.27.3.4
157.
Freescale Semiconductor
Address 0x0001
Address 0x0002
Address 0x0003
Reset
Reset
Reset
DDRA
W
W
W
R
R
Field
R
5-0
Read: Anytime.
Read: Anytime.
Read: Anytime.
Write: Unimplemented. Writing to this register has no effect.
Write: Anytime.
Write: Unimplemented. Writing to this register has no effect.
Port A Data Direction—
This register controls the data direction of pins 5 through 0.
The SPI function controls the data direction for the associated pins. In this case the data direction bits will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
PIM Reserved Register
Port A Data Direction Register (DDRA)
PIM Reserved Register
7
0
0
7
0
0
7
0
0
6
0
0
6
0
0
6
0
0
DDRA5
0
0
0
0
0
5
5
5
DDRA4
0
0
0
0
0
4
4
4
Description
DDRA3
0
0
0
0
0
3
3
3
Port Integration Module (9S12I32PIMV1)
DDRA2
0
0
0
0
0
2
2
2
Access: User read/write
DDRA1
0
0
0
0
0
1
1
1
Access: User read
Access: User read
MM912F634
DDRA0
0
0
0
0
0
0
0
0
169
(155)
(156)
(157)