MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 326

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.38.4.3.3
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge
clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle
transfer operation.
The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the
slave to transfer its first data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave.
When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI
shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin
of the master to the serial input pin on the slave.
This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting
taking place on odd numbered edges.
Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the
parallel SPI data register after the last bit is shifted in.
After the 16th SCK edge:
Figure 104
because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output
from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin
of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
Freescale Semiconductor
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Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was
in the data register of the slave is in the master.
The SPIF flag bit in SPISR is set indicating that the transfer is complete.
shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram
CPHA = 1 Transfer Format
Serial Peripheral Interface (S12SPIV4)
MM912F634
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