MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 263

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.35
4.35.1
This section describes the functionality of the Computer Operating Properly module (COP), a sub-block of the HCS12S core
platform.The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly.
If the COP times out a system reset is initiated. Two types of COP operation are available: Window COP or Normal COP
When COP is enabled, sequential writes of $55 and $AA (in this order) are expected to the ARMCOP register during the selected
timeout period. Once this is done, the COP timeout period restarts. If the program fails to do this the S12SCRG will initiate a reset.
4.35.1.1
A block diagram of the COP is shown in
4.35.1.2
The COP includes these distinctive features:
Freescale Semiconductor
Int_Ref_Clock
•
•
•
•
•
Watchdog timer with a timeout clear window.
Default maximum COP rate and no Window COP in Special Single Chip mode after system reset.
Auto COP rate load after system reset in SoC Normal mode. (For source of COP rate bits please refer to the Device
User Guide)
Software selectable COP operation in WAIT and STOP mode.
Customer selectable COP off while BDM active (debugging session).
SSC_Mode
Computer Operating Properly (S12SCOPV1)
Introduction
Overview
Features
Modulus Down Counter
(2
6
CR[2:0]
,..., 2
16
)
Figure 81
Figure 82. Block Diagram
ARMCOP-Register
WCOP
Computer Operating Properly (S12SCOPV1)
Control Logic
COP reset
MM912F634
request
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