MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 306

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 394. D2DI Status Register 1 (D2DSTAT1) (continued)
Table 396. D2DI Address Buffer Register (D2DADR)
Functional Description and Application Information
Table 395. D2DSTAT1 Register Field Descriptions
4.37.3.2.5
This read-only register contains information about the ongoing D2D interface transaction. The register content will be updated
when a new transaction starts. In error cases the user can track back, which transaction failed.
Table 397. D2DI Address Buffer Register Bit Descriptions
Freescale Semiconductor
0x00DC / 0x00DD
D2DBSY
ADR[7:0]
Reset
Reset
D2DIF
NBLK
Field
Field
RWB
W
11:8
SZ8
R
W
R
5:0
7:0
15
14
13
12
7
6
RWB
D2D Interrupt Flag — This read-only flag reflects the status of the D2DINT Pin. The D2D interrupt flag can only be cleared by a
target specific interrupt acknowledge sequence.
0 External Interrupt is negated
1 External Interrupt is asserted
D2D Initiator Busy — This read-only status bit indicates that a D2D transaction is ongoing.
0 D2D initiator idle.
1 D2D initiator transaction ongoing.
Reserved, should be masked to ensure compatibility with future versions of this interface.
Transaction Read-Write Direction — This read-only bit reflects the direction of the transaction
0 Write Transaction
1 Read Transaction
Transaction Size — This read-only bit reflects the data size of the transaction
0 16-bit transaction.
1 8-bit transaction.
Reserved, should be masked to ensure compatibility with future versions of this interface.
Transaction Mode — This read-only bit reflects the mode of the transaction
0 Blocking transaction.
1 Non-blocking transaction.
Reserved, should be masked to ensure compatibility with future versions of this interface.
Transaction Address — Those read-only bits contain the address of the transaction
15
0
D2DIF
0
D2DI Address Buffer Register (D2DADR)
SZ8
14
0
13
D2DBSY
0
0
0
NBLK
12
0
11
0
0
0
0
10
0
0
0
0
9
0
0
Description
Description
0
0
8
0
7
0
0
0
6
5
0
0
0
0
4
ADR[7:0]
Die-to-Die Initiator (D2DIV1)
0
3
0
0
0
2
Access: User read
MM912F634
1
0
0
0
0
0
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