MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 265

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.35.3.2.1
This register controls the COP (Computer Operating Properly) watchdog.
Table 342. COP Control Register (COPCTL)
Read: Anytime
Write:
The COP timeout period is restarted if one these two conditions are true:
Table 343. COPCTL Field Descriptions
Freescale Semiconductor
0x003E
Note:
Reset
186.
WRTMASK
COPSWAI
RSBCK
W
WCOP
R
1.
2.
1.
2.
Field
(186)
7
6
5
4
Refer to Device User Guide
RSBCK: anytime in special modes; write to “1” but not to “0” in all other modes
WCOP, CR2, CR1, CR0:
— Anytime in special modes
— Write once in all other modes
Writing a non-zero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0.
Changing RSBCK bit from “0” to “1”.
see note
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A
write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, $55 can be
written as often as desired. Once $AA is written after the $55, the timeout logic restarts and the user must wait until the next
window before writing to ARMCOP.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP, CR[2:0], COPSWAI and
COPRSTP bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of
WCOP, CR[2:0], COPSWAI, and COPRSTP.
0 Write of WCOP, CR[2:0], COPSWAI and COPRSTP has an effect with this write of COPCTL
1 Write of WCOP, CR[2:0], COPSWAI and COPRSTP has no effect with this write of COPCTL.
COP Stops in Wait mode bit
Normal modes: Write once
Special modes: Write anytime
0 COP continues in Wait mode.
1 COP stops and initializes the COP counter whenever the part enters Wait mode.
7
or
(Does not count for “write once”)
COP Control Register (COPCTL)
RSBCK
0
6
(Section 4.35.4.1, “COP
WRTMASK
5
0
0
Table 344
Configuration") for reset values of WCOP, CR2, CR1 and CR0.
shows the duration of this window for the seven available COP rates.
COPSWAI
0
4
Description
COPRSTP
0
3
Computer Operating Properly (S12SCOPV1)
see note
CR2
2
see note
CR1
1
MM912F634
see note
CR0
0
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