MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 93

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 111. PWMCTL - Register Field Descriptions
Functional Description and Application Information
4.13.3.1.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1),
the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM
output until its clock source begins its next cycle, due to the synchronization of PWMEx and the clock source.
4.13.3.1.2
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit. If the polarity bit is one, the
PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the
polarity bit is zero, the output starts low and then goes high when the duty count is reached.
4.13.3.1.3
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described by the following.
Freescale Semiconductor
PWME[1:0]
PPOL[1:0]
CAE[1:0]
PCLK1
PCLK0
Field
7–6
3–2
1-0
5
4
Center Aligned Output Modes on Channels 1–0
0 Channels 1–0 operate in left aligned output mode.
1 Channels 1–0 operate in center aligned output mode.
Pulse Width Channel 1 Clock Select
0 Clock B is the clock source for PWM channel 1.
1 Clock SB is the clock source for PWM channel 1.
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
Pulse Width Channel 1–0 Polarity Bits
0 PWM channel 1–0 outputs are low at the beginning of the period, then go high when the duty count is reached.
1 PWM channel 1–0 outputs are high at the beginning of the period, then go low when the duty count is reached.
Pulse Width Channel 1–0 Enable
0 Pulse width channel 1–0 is disabled.
1 Pulse width channel 1–0 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock
source begins its next cycle.
PWM Enable (PWMEx)
The first PWM cycle after enabling the channel can be irregular. If both PWM channels are
disabled (PWME1–0 = 0), the prescaler counter shuts off for power savings.
PWM Polarity (PPOLx)
PPOLx register bits can be written anytime. If the polarity changes while a PWM signal is
being generated, a truncated or stretched pulse can occur during the transition
PWM Clock Select (PCLKx)
Register bits PCLK0 and PCLK1 can be written anytime. If a clock select changes while a
PWM signal is being generated, a truncated or stretched pulse can occur during the
transition.
NOTE
NOTE
NOTE
Description
PWM Control Module (PWM8B2C)
MM912F634
93