MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 192

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 248. IVBR Field Descriptions
4.29.4
The 9S12I32PIMV1 module processes all exception requests to be serviced by the CPU module. These exceptions include
interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in
the subsections below.
4.29.4.1
The CPU handles both reset requests and interrupt requests. A priority decoder is used to evaluate the priority of pending
interrupt requests.
4.29.4.2
The 9S12I32PIMV1 module contains a priority decoder to determine the priority for all interrupt requests pending for the CPU. If
more than one interrupt request is pending, the interrupt request with the higher vector address wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
Since an interrupt vector is only supplied at the time when the CPU requests it, it is possible that a higher priority interrupt request
could override the original interrupt request that caused the CPU to request the vector. In this case, the CPU will receive the
highest priority vector and the system will process this interrupt request first, before the original interrupt request is processed.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has
been recognized, but prior to the CPU vector request), the vector address supplied to the CPU will default to that of the spurious
interrupt vector.
4.29.4.3
The 9S12I32PIMV1 module supports three system reset exception request types (please refer to CRG for details):
Freescale Semiconductor
IVB_ADDR[7:0]
1.
2.
3.
1.
Field
7–0
The local interrupt enabled bit in the peripheral module must be set.
The I bit in the condition code register (CCR) of the CPU must be cleared.
There is no SWI, TRAP, or X bit maskable request pending.
Pin reset, power-on reset or illegal address reset
Functional Description
S12S Exception Requests
Interrupt Prioritization
Reset Exception Requests
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of reset these bits
are set to 0xFF (i.e., vectors are located at 0xFF80–0xFFFE) to ensure compatibility to HCS12.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of IVBR are
All non I bit maskable interrupt requests always have higher priority than the I bit maskable
interrupt requests. If the X bit in the CCR is cleared, it is possible to interrupt an I bit
maskable interrupt by an X bit maskable interrupt. It is possible to nest non maskable
interrupt requests, e.g., by nesting SWI or TRAP calls.
Care must be taken to ensure that all interrupt requests remain active until the system
begins execution of the applicable service routine. Otherwise, the exception request may not
get processed at all or the result may be a spurious interrupt request (vector at address
(vector base + 0x0080)).
vector address. Therefore, changing the IVBR has no effect on the location of the three reset vectors
(0xFFFA–0xFFFE).
ignored and the upper byte of the vector address is fixed as “0xFF”. This is done to enable handling of all
non-maskable interrupts in the BDM firmware.
NOTE
Description
Interrupt Module (S12SINTV1)
MM912F634
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