MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 307

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 398. D2DI Data Buffer Register (D2DDATA)
Functional Description and Application Information
4.37.3.2.6
This read-only register contains information about the ongoing D2D interface transaction. For a write transaction, the data
becomes valid at the begin of the transaction. For a read transaction, the data will be updated during the transaction, and is
finalized when the transaction is acknowledged by the target. In error cases, the user can track back what has happened.
Table 399. D2DI Data Buffer Register Bit Descriptions
Both D2DDATA and D2DADR can be read with byte accesses.
4.37.4
4.37.4.1
Out of reset the interface is disabled. The interface must be initialized by setting the interface clock speed, the timeout value, the
transfer width, and finally enabling the interface. This should be done using a 16-bit write, or if using 8-bit write, D2DCTL1 must
be written before D2D2CTL0.D2DEN = 1 is written. Once it is enabled in normal modes, only a reset can disable it again (write
once feature).
4.37.4.2
A transaction on the D2D Interface is triggered by writing to either the 256 byte address window or reading from the address
window (see STAA/LDAA 0/1 in the next figure). Depending on which address window is used, a blocking or a non-blocking
transaction is performed. The address for the transaction is the 8-bit wide window relative address. The data width of the CPU
read or write instructions determines if 8-bit or 16-bit wide data are transferred. There is always only one transaction active.
Figure 96
For all 16-bit read/write accesses of the CPU, the addresses are assigned according the big-endian model:
addr: byte-address (8 bit wide) inside the blocking or non-blocking window, as provided by the CPU and transferred to the D2D
target word: CPU data, to be transferred from/to the D2D target
The application must care for the stretched CPU cycles (limited by the TIMOUT value, caused by blocking or consecutive
accesses), which could affect time limits, including COP (computer operates properly) supervision. The stretched CPU cycles
cause the “CPU halted” phases (see
Freescale Semiconductor
0x00DE / 0x00DF
Reset
DATA
Field
15:0
W
R
word [15:8]: addr
shows the various types of transactions explained in more detail below.
Transaction Data — Those read-only bits contain the data of the transaction
15
0
Functional Description
Initialization
Transactions
D2DI Data Buffer Register (D2DDATA)
14
0
13
0
12
0
Figure
word[7:0]: addr+1
11
0
96).
10
0
0
9
Description
DATA15:0
0
8
0
7
0
6
5
0
0
4
Die-to-Die Initiator (D2DIV1)
0
3
0
2
Access: User read
MM912F634
1
0
0
0
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