MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 320

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 411. SPISR Field Descriptions
4.38.3.2.5
Table 412. SPI Data Register (SPIDR)
Read: Anytime; normally read only when SPIF is set
Write: Anytime
Freescale Semiconductor
0x00ED
Reset
W
SPTEF
R
MODF
Field
SPIF
7
5
4
The SPI data register is both the input and output register for SPI data. A write to this register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the
previous transmission has completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the
SPI data register is ready to accept new data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and a byte has been received, the received byte is transferred from the receive shift register to the
SPIDR and SPIF is set.
If SPIF is set and not serviced, and a second byte has been received, the second received byte is kept as valid byte in
the receive shift register until the start of another transmission. The byte in the SPIDR does not change.
If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of a third transmission,
the byte in the receive shift register is transferred into the SPIDR and SPIF remains set (see
If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of a third transmission,
the byte in the receive shift register has become invalid and is not transferred into the SPIDR (see
Bit 7
SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register. This bit is
cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register.
0 Transfer not yet complete.
1 New data copied to SPIDR.
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear this bit and
place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write to SPIDR. Any write to the
SPI data register without reading SPTEF = 1, is effectively ignored.
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag — This bit is set if the SS input becomes low, while the SPI is configured as a master and mode fault detection
is enabled, the MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Register 2
write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
0
7
SPI Data Register (SPIDR)
(SPICR2)"”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a
6
0
6
5
5
0
4
0
4
Description
3
0
3
Serial Peripheral Interface (S12SPIV4)
2
0
2
Section 4.38.3.2.2, “SPI Control
Figure
1
2
0
Figure
100).
MM912F634
101).
Bit 0
0
0
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