MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 51

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Freescale Semiconductor
Table 65. Analog die Registers
0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 (continued)
Note:
Offset
0xCA
0xCB
0xCC
0xCD
0xCE
0xC8
0xC9
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xF0
0xF1
0xF2
0xF3
0xF4
60.
Registers not shown are reserved and must not be accessed.
Timer System Control Reg 2
TIM InCap/OutComp Reg 0
TIM InCap/OutComp Reg 0
TIM InCap/OutComp Reg 1
TIM InCap/OutComp Reg 1
TIM InCap/OutComp Reg 2
TIM InCap/OutComp Reg 2
TIM InCap/OutComp Reg 3
TIM InCap/OutComp Reg 3
Timer Interrupt Enable Reg
Main Timer Interrupt Flag 1
Main Timer Interrupt Flag 2
Silicon Revision Register
Timer Control Register 1
Timer Control Register 2
Trimming Reg 0
Trimming Reg 1
Trimming Reg 2
Trimming Reg 3
TC0 (hi)
TC0 (lo)
TC1 (hi)
TC1 (lo)
TC2 (hi)
TC2 (lo)
TC3 (hi)
TC3 (lo)
TSCR2
TCTL1
TCTL2
TFLG1
TFLG2
Name
CTR0
CTR1
CTR2
CTR3
SRR
TIE
(60)
- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
OFFCTRE OFFCTR2 OFFCTR1 OFFCTR0 CTR3_E
LINTRE
EDG3B
BGTRE
tc0 15
tc1 15
tc2 15
tc3 15
OM3
tc0 7
tc1 7
tc2 7
tc3 7
TOF
TOI
7
0
0
0
0
CTR1_6
EDG3A
LINTR
tc0 14
tc1 14
tc2 14
tc3 14
tc0 6
tc1 6
tc2 6
tc3 6
OL3
6
0
0
0
0
0
0
BGTRIMU
WDCTRE
EDG2B
tc0 13
tc1 13
tc2 13
tc3 13
tc0 5
tc1 5
tc2 5
tc3 5
OM2
5
0
0
0
0
P
0
0
BGTRIMD
SLPBGTR
CTR0_4
EDG2A
tc0 12
tc1 12
tc2 12
tc3 12
tc0 4
tc1 4
tc2 4
tc3 4
OL2
N
4
0
0
0
0
E
0
SLPBG_L
IREFTRE IREFTR2
CTR0_3
EDG1B
TCRE
tc0 11
tc1 11
tc2 11
tc3 11
OM1
tc0 3
tc1 3
tc2 3
tc3 3
OCK
C3F
C3I
3
0
FMREV
SLPBGTR
WDCTR2 WDCTR1 WDCTR0
CTR3_2
EDG1A
tc0 10
tc1 10
tc2 10
tc3 10
tc0 2
tc1 2
tc2 2
tc3 2
OL1
PR2
C2F
C2I
2
0
2
SLPBGTR
IREFTR1
CTR3_1
EDG0B
OM0
tc0 9
tc0 1
tc1 9
tc1 1
tc2 9
tc2 1
tc3 9
tc3 1
PR1
C1F
C1I
1
0
1
MMREV
Introduction
MM912F634
SLPBGTR
IREFTR0
CTR3_0
EDG0A
tc0 8
tc0 0
tc1 8
tc1 0
tc2 8
tc2 0
tc3 8
tc3 0
OL0
PR0
C0F
C0I
0
0
0
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