MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 129

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Freescale Semiconductor
Table 151. Module Memory Map (continued)
Note:
112.
113.
114.
111.
Offset
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Always read $00.
Only writable in special modes. (Refer to SOC Guide for different modes).
Write to these registers have no meaning or effect during input capture.
0xCC
0xCD
0xC8
0xC9
0xCA
0xCB
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
(111)
Timer Input Capture/Output Compare Register 0 (TC0(hi))
Timer Input Capture/Output Compare Register 0 (TC0(lo))
Timer Input Capture/Output Compare Register 1 (TC1(hi))
Timer Input Capture/Output Compare Register 1 (TC1(lo))
Timer Input Capture/Output Compare Register 2 (TC2(hi))
Timer Input Capture/Output Compare Register 2 (TC2(lo))
Timer Input Capture/Output Compare Register 3 (TC3(hi))
Timer System Control Register 2 (TSCR2)
Timer Interrupt Enable Register (TIE)
Main Timer Interrupt Flag 1 (TFLG1)
Main Timer Interrupt Flag 2 (TFLG2)
Timer Control Register 1 (TCTL1)
Timer Control Register 2 (TCTL2)
Use
Basic Timer Module - TIM (TIM16B4C)
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
MM912F634
(114)
(113)
(113)
(113)
(113)
(113)
(113)
129