MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 231

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.3.2.8.8
Table 307. Debug Comparator Data Low Mask Register (DBGADLM)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
Table 308. DBGADLM Field Descriptions
4.31.4
This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can
generate breakpoints, but tracing is not possible.
4.31.4.1
Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer, and
generation of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state
sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity.
Comparator A can also be configured to monitor databus activity and mask out individual data bus bits during a compare.
Comparators can be configured to use R/W and word/byte access qualification in the comparison. A match with a comparator
register value can initiate a state sequencer transition to another state (see
possible. Using a forced match, a state sequencer transition can occur immediately on a successful match of system busses and
comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only if the instruction reaches
the execution stage of the instruction queue, can a state sequencer transition occur. In the case of a transition to Final State, bus
tracing is triggered and/or a breakpoint can be generated.
A state sequencer transition to Final State (with associated breakpoint, if enabled) can be initiated by writing to the TRIG bit in
the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map, and must be read out using standard 16-bit word
reads.
Freescale Semiconductor
Address: 0x002F
Reset
Bits[7:0]
W
R
Field
7–0
Functional Description
Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares
the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG
bit in DBGACTL is clear
0 Do not compare corresponding data bit. Any value of corresponding data bit allows match
1 Compare corresponding data bit
Bit 7
S12SDBGV1 Operation
0
7
Debug Comparator Data Low Mask Register (DBGADLM)
Bit 6
0
6
Bit 5
5
0
Bit 4
0
4
Description
Bit 3
0
3
Figure
71). Either forced or tagged matches are
Bit 2
S12S Debug (S12SDBGV1) Module
0
2
Bit 1
1
0
MM912F634
Bit 0
0
0
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