MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 328

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are
010, the divisor is multiplied by 3, etc. See
clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by
6, divide by 10, etc.
The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases,
the divider is disabled to decrease I
4.38.4.5
4.38.4.5.1
The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during
idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external
device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in
Table
The mode fault feature is disabled while SS output is enabled.
4.38.4.5.2
The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see
only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes
the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode.
The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.
Freescale Semiconductor
403.
Special Features
SS Output
Care must be taken when using the SS output feature in a multi master system because the
mode fault feature is not available for detecting system errors between masters.
Bidirectional Mode (MOMI or SISO)
In bidirectional master mode, with mode fault enabled, both MISO and MOSI data pins can
be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional
mode, and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically
switched to slave mode. In this case, MISO becomes occupied by the SPI and MOSI is not
used. This must be considered if the MISO pin is used for another purpose.
DD
current.
Table 409
for baud rate calculations for all bit conditions, based on a 20 MHz bus
NOTE
NOTE
Serial Peripheral Interface (S12SPIV4)
Table
413). In this mode, the SPI uses
MM912F634
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