MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 321

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.38.4
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can
poll the SPI status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated
SPI port pins are dedicated to the SPI function as:
The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in
the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed,
this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master
and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master
SPI data register after a transfer operation is the input data from the slave.
A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is
complete and SPIF is cleared, received data is moved into the receive data register. This 8-bit data register acts as the SPI
Freescale Semiconductor
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Slave select (SS)
Serial clock (SCK)
Master out/slave in (MOSI)
Master in/slave out (MISO)
Receive Shift Register
Receive Shift Register
Functional Description
SPI Data Register
SPI Data Register
SPIF
SPIF
Data A Received
Data A Received
Figure 101. Reception with SPIF Serviced Too Late
= Unspecified
Figure 100. Reception with SPIF Serviced in Time
= Unspecified
Data A
Data A
Data A
Data A
= Reception in progress
Data B Received
= Reception in progress
Data B Received
Data B
Data B
Data B Lost
SPIF Serviced
SPIF Serviced
Serial Peripheral Interface (S12SPIV4)
Data B
Data C Received
Data C Received
Data C
Data C
Data C
Data C
MM912F634
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