MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 119

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.15.3.2
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and
idle characters. The transmitter block diagram is shown in
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter output is inverted by
setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIC2. This queues a preamble character that is one full
character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs
store data into the transmit data buffer by writing to the SCI data register (SCID).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting
in the M control bit. For the remainder of this section, we will assume M = 0, selecting the normal 8-bit data mode. In 8-bit data
mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new SCI
character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock)
and the transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data
buffer at SCID.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit
complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress
must first be completed. This includes data characters in progress, queued idle characters, and queued break characters.
4.15.3.2.1
The SBK control bit in SCIC2 is used to send break characters which were originally used to gain the attention of old teletype
receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of
13 bit times can be enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break
character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter
(synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale
Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE = 1) occurs.
When idle-line wake-up is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping
receivers. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the
transmit shifter, then write 0 and then write 1 to the TE bit. This action queues an idle character to be sent as soon as the shifter
is available. As long as the character in the shifter does not finish while TE = 0, the SCI transmitter never actually releases control
of the TxD pin. If there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin that is
shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal idle line even if the SCI loses
control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
Freescale Semiconductor
Transmitter Functional Description
Send Break and Queued Idle
Table 139. Break Character Length
BRK13
0
0
1
1
M
0
1
0
1
Figure
31.
Break Character Length
10 bit times
13 bit times
14 bit times
11 bit times
Serial Communication Interface (S08SCIV4)
MM912F634
119