MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 136

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 177. Main Timer Interrupt Flag 1 (TFLG1)
Note:
Functional Description and Application Information
4.18.3.3.12
Offset
126.
Freescale Semiconductor
Table 175. TIE - Register Field Descriptions (continued)
Table 178. TFLG1 - Register Field Descriptions
Reset
W
R
(126)
PR[2:0]
C[3:0]F
TCRE
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Field
3-0
3-0
3
0xCC
7
0
0
TCRE — Timer Counter Reset Enable
1 = Enables Timer Counter reset by a successful output compare on channel 3
0 = Inhibits Timer Counter reset and counter continues to run.
Timer Prescaler Select
These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in
Input Capture/Output Compare Channel Flag.
1 = Input Capture or Output Compare event occurred
0 = No event (Input Capture or Output Compare event) occurred.
Main Timer Interrupt Flag 1 (TFLG1)
These flags are set when an input capture or output compare event occurs. Flag set on a
particular channel is cleared by writing a one to that corresponding CnF bit. Writing a zero
to CnF bit has no effect on its status. When TFFCA bit in TSCR register is set, a read from
an input capture or a write into an output compare channel will cause the corresponding
channel flag CnF to be cleared.
Table 176. Timer Clock Selection
PR2
0
0
0
0
1
1
1
1
6
0
0
0
0
5
PR1
0
0
1
1
0
0
1
1
NOTE
0
0
4
PR0
Description
Description
0
1
0
1
0
1
0
1
C3F
0
3
D2D Clock / 128
D2D Clock / 16
D2D Clock / 32
D2D Clock / 64
D2D Clock / 1
D2D Clock / 2
D2D Clock / 4
D2D Clock / 8
Timer Clock
Basic Timer Module - TIM (TIM16B4C)
C2F
0
2
C1F
1
0
Access: User read/write
Table
MM912F634
176.
C0F
0
0
136