MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 204

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.30.4.5
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word
depending on the command. All the read commands return 16-bits of data despite the byte or word implication in the command
name.
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before
attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted
out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before
attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The
150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free
cycle before stealing a cycle.
For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and
before attempting to obtain the read data. The 48 cycle wait allows enough time for the requested data to be made available in
the BDM shift register, ready to be shifted out.
For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before
attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed.
The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial
command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the
user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup
table.
Figure 61
edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is
8  16 target clock cycles. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See
Freescale Semiconductor
represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling
BDM Command Structure
If the bus rate of the target processor is unknown or could be changing, it is recommended
that the ACK (acknowledge function) is used to indicate when an operation is complete.
When using ACK, the delay times are automated.
8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an
even address, the valid data will appear in the MSB. If reading an odd address, the valid data
will appear in the LSB.
16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware
command, the BDM will ignore the least significant bit of the address and will assume an
even address from the remaining bits.
NOTE
Background Debug Module (S12SBDMV1)
Section 4.30.4.6,
MM912F634
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