MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 158

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.26
4.26.1
The MC9S12I32 micro controller implemented in the MM912F634 is the first member of the newly introduced S12S
platform, mainly targeted for Intelligent Distributed Control (IDC) applications. The MC9S12I32 device is designed as counter part
to an analog die, and is not being offered as a standalone MCU.
The MC9S12I32 die contains a HCS12 Central Processing Unit (CPU), offering 32 kB of Flash memory and 2.0 kB of system
SRAM, up to six general purpose I/Os, an on-chip oscillator and clock multiplier, one Serial Peripheral Interface (SPI), an interrupt
module, and debug capabilities via the on-chip debug module (DBG) in combination with the Background Debug Mode (BDM)
interface. The MC9S12I32 die has no external bus interface, and thus no emulation capability as well as no internal voltage
regulator. Additionally there is a die-to-die initiator (D2DI) which represents the communication interface to the companion
(analog) die.
4.26.1.1
Freescale Semiconductor
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16-Bit S12S CPU
— Upward compatible with the CPU12 instruction set
INT (interrupt module)
— Supporting nested interrupts
MMC (memory mapping control and crossbar switch)
DBG (debug module)
— Monitoring of the CPU bus with tag-type or force-type breakpoint requests
— 64 x 20-bit circular trace buffer captures change-of-flow or memory access information
BDM (background debug mode)
OSC (oscillator)
— Full-swing Pierce oscillator option utilizing a 4.0 MHz to 16 MHz crystal or resonator
CRG (clock and reset generation)
— 32 kHz trimmable internal reference clock
— Oscillator clock monitor
— Internal Digital Controlled Oscillator (DCO), Frequency Locked Loop (FLL) based
COP module (Computer Operating Properly watchdog)
RTI module (Real Time Interrupt)
Memory Options
— 32 k byte Flash
— 2.0 k byte RAM
Flash General Features
— Erase sector size 512 bytes
— Automated program and erase algorithm
Serial Peripheral Interface Module (SPI)
— Configurable for 8 or 16-bit data size
Input/Output
— Up to 6 general-purpose input/output (I/O) pins
— Hysteresis on all input pins
— Configurable drive strength on all output pins
Die 2 Die Initiator (D2DI)
— Up to 2.0 Mbyte/s data rate
— Configurable 4-bit or 8-bit wide data path
20 MHz maximum CPU bus frequency (16 MHz for MM912F634CV2AP)
MM912F634 -
Introduction
Features
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Note: Five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) are not supported on
this device.
MCU Die Overview
MM912F634 - MCU Die Overview
MM912F634
MCU
ANALOG
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