MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 75

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Note:
Functional Description and Application Information
4.8.2
4.8.2.1
Table 85. Wake-up Control Register (WCR)
Table 86. WCR - Register Field Descriptions
Freescale Semiconductor
Offset
72.
Reset
W
R
5 - L5WE
4 - L4WE
3 - L3WE
1 - L1WE
0 - L0WE
2- L2WE
CSSEL
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
(72)
7-6
0x12
Register Definition
0
7
Cyclic Sense Select - Configures the HSx output for the cyclic sense event. Note, with no LxWE selected - only the selected
HSx output will be switched periodically, no Lx state change would be detected. For all configurations, the Forced Wake-up
can be activated in parallel in
00 - Cyclic Sense Off
01 - Cyclic Sense with periodic HS1on
10 - Cyclic Sense with periodic HS2 on
11 - Cyclic Sense with periodic HS1 and HS2 on.
Wake-up Input 5 Enabled - L5 Wake-up Select Bit.
0 - L5 Wake-up Disabled
1 - L5 Wake-up Enabled
Wake-up Input 4 Enabled - L4 Wake-up Select Bit.
0 - L4 Wake-up Disabled
1 - L4 Wake-up Enabled
Wake-up Input 3 Enabled - L3 Wake-up Select Bit.
0 - L3Wake-up Disabled
1 - L3 Wake-up Enabled
Wake-up Input 2 Enabled - L2 Wake-up Select Bit.
0 - L2 Wake-up Disabled
1 - L2 Wake-up Enabled
Wake-up Input 1 Enabled - L1 Wake-up Select Bit.
0 - L1 Wake-up Disabled
1 - L1 Wake-up Enabled
Wake-up Input 0 Enabled - L0 Wake-up Select Bit.
0 - L0 Wake-up Disabled
1 - L0 Wake-up Enabled
Wake-up Control Register (WCR)
CSSEL
0
6
Section 4.8.2.2, “Timing Control Register (TCR)"
L5WE
5
1
L4WE
4
1
Description
L3WE
1
3
L2WE
1
2
Wake-up / Cyclic Sense
L1WE
1
1
Access: User read/write
MM912F634
L0WE
1
0
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