MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 197

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.30.2
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system.
During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin
becomes the dedicated serial interface pin for the background debug mode. The communication rate of this pin is based on the
DCO clock or external reference clock depending on the configuration selected (please refer to the S12S_CRG Block Guide for
more details) which gets divided by five. Hence the BDM serial interface clock is always DCO clock divided by five after reset in
to Special Single Chip mode which is about 6.4 MHz. After reset the BDM communication rate can be modified either via BDM
command or CPU user code. When modifying the DCO clock please make sure that the communication rate is adapted
accordingly and a communication timeout (BDM soft reset) has occurred.
4.30.3
4.30.3.1
Table 250
4.30.3.2
A summary of the registers associated with the BDM is shown in
communications to the BDM hardware using READ_BD and WRITE_BD commands.
Freescale Semiconductor
0x3_FF00
0x3_FF01
0x3_FF02
0x3_FF03
0x3_FF04
0x3_FF05
0x3_FF06
0x3_FF07
Address
Global
Table 250. BDM Memory Map
shows the BDM memory map when BDM is active.
0x3_FF0C–0x3_FF0E
External Signal Description
Memory Map and Register Definition
0x3_FF00–0x3_FF0B
0x3_FF10–0x3_FFFF
BDMCCR
Reserved
BDMSTS
Reserved
Reserved
Reserved
Reserved
Reserved
Register
Module Memory Map
Register Descriptions
Global Address
Name
0x3_FF0F
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
ENBDM
CCR7
Bit 7
X
X
X
X
X
0
BDMACT
Figure 60. BDM Register Summary
CCR6
X
X
X
X
X
6
0
Family ID (part of BDM firmware ROM)
CCR5
BDM firmware ROM
BDM firmware ROM
X
X
X
X
X
5
0
0
BDM registers
Module
Figure
CCR4
SDV
4
X
X
X
X
X
0
60. Registers are accessed by host-driven
TRACE
Background Debug Module (S12SBDMV1)
CCR3
3
X
X
X
X
X
0
CCR2
2
X
0
X
X
X
X
0
Size (Bytes)
240
UNSEC
12
CCR1
3
1
X
X
X
X
1
0
0
MM912F634
CCR0
Bit 0
X
X
X
X
0
0
0
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