MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 266

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 343. COPCTL Field Descriptions (continued)
Freescale Semiconductor
COPRSTP
CR[2:0]
Field
2–0
3
COP Runs in Stop Mode Bit
Normal modes: Write once
Special modes: Write anytime
0 COP stops in Stop mode
1 COP continues in Stop mode
Note: If the COPRSTP bit is cleared the COP counter will go static while in Stop mode. The COP counter will not initialize like
COP Watchdog Timer Rate Select Bits — These bits select the COP timeout rate (see
to CR[2:0] enables the COP counter and starts the timeout period. A COP counter timeout causes a system reset. This can be
avoided by periodically (before timeout) re-initialize the COP counter via the ARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest timeout
period (2
Table 344. COP Watchdog Rates
Note:
187.
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in special mode
in Wait mode with COPSWAI bit set.
CR2
16
Refer to Device User Guide
CR2, CR1 and CR0.
0
0
0
0
1
1
1
1
cycles) in normal COP mode (Window COP mode disabled):
CR1
0
0
1
1
0
0
1
1
(Section 4.35.4.1, “COP
(187)
CR0
0
1
0
1
0
1
0
1
Description
Configuration") for reset values of WCOP,
Input_CLK Cycles to Timeout
Computer Operating Properly (S12SCOPV1)
COP disabled
2
2
2
2
2
2
2
10
12
14
15
16
6
8
Table
344). Writing a non-zero value
MM912F634
266