MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 116

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 134. SCI Status Register 2 (SCIS2)
Note:
Functional Description and Application Information
Table 133. SCIS1 Field Descriptions (continued)
4.15.2.5
This register has one read-only status flag.
Offset
101.
Table 135. SCIS2 Field Descriptions
Freescale Semiconductor
Note:
102.
Reset
RXINV
RXEDGIF
W
R
LBKDIF
RWUID
LBKDE
BRK13
Field
Field
(101)
FE
PF
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
1
0
7
6
4
3
2
1
Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
(102)
0x45
LBKDIF
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was
expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIS1 with FE = 1 and
then read the SCI data register (SCID).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received
character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the SCI data register (SCID).
0 No parity error.
1 Parity error.
LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is
detected. LBKDIF is cleared by writing a “1” to it.
0 No LIN break character has been detected.
1 LIN break character has been detected.
RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the
RxD pin occurs. RXEDGIF is cleared by writing a “1” to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
Receive Data Inversion — Setting this bit reverses the polarity of the received data input.
0 Receive data not inverted
1 Receive data inverted
Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit.
0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
Break Character Generation Length — BRK13 is used to select a longer transmitted break character length. Detection of a
framing error is not affected by the state of this bit.
0 Break character is transmitted with length of 10 bit times (11 if M = 1)
1 Break character is transmitted with length of 13 bit times (14 if M = 1)
LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing
error (FE) and receive data register full (RDRF) flags are prevented from setting.
0 Break character detection disabled
1 Break character detection enabled
SCI Status Register 2 (SCIS2)
7
0
RXEDGIF
6
0
0
0
5
RXINV
0
4
(92)
Description
Description
RWUID
0
3
Serial Communication Interface (S08SCIV4)
BRK13
0
2
LBKDE
1
0
Access: User read/write
MM912F634
RAF
0
0
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