MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 295

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.36.4.3
4.36.4.3.1
The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed,
causing the command write sequence to immediately abort:
Freescale Semiconductor
1.
2.
3.
4.
5.
6.
7.
8.
Writing to a Flash address before initializing the FCLKDIV register.
Writing a byte or misaligned word to a valid Flash address.Writing to any Flash register other than FCMD after writing
to a Flash address.
Writing to a second Flash address in the same command write sequence.
Writing an invalid command to the FCMD register, unless the address written was in a protected area of the Flash array.
Writing a command other than burst program, while CBEIF is set and CCIF is clear.
When security is enabled, writing a command other than erase verify or mass erase to the FCMD register, when the
write originates from a non-secure memory location or from the background debug mode.
Writing to a Flash address after writing to the FCMD register.
Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register.
Illegal Flash Operations
Flash Access Violations
Clock Register
Written
Check
Bit Polling for
Command Completion
Check
Command
Buffer Empty Check
Access Error and
Protection Violation
Check
Figure 91. Example Set Verify Margin Level Command Flow (Special Mode only)
Read: FCLKDIV register
2.
3.
1.
yes
FDIVLD
START
Write: FCMD register
Set Verify Margin Level Command 0x75
Write: FSTAT register
Clear CBEIF 0x80
Write: Flash Memory Address
and Data to Set Verify Margin Level
Set?
Read: FSTAT register
Read: FSTAT register
ACCERR/PVIOL
yes
CBEIF
yes
no
CCIF
Set?
Set?
EXIT
Write: FCLKDIV register
Set?
no
no
yes
no
Write: FSTAT register
Clear ACCERR/PVIOL 0x30
NOTE: FCLKDIV needs to
be set after each reset
32 kbyte Flash Module (S12SFTSR32KV1)
MM912F634
295