MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 308

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.37.4.2.1
When writing to the address window associated with blocking transactions, the CPU is held until the transaction is completed,
before completing the instruction.
example.
Blocking writes should be used when clearing interrupt flags located in the target, or other writes which require that the operation
at the target is completed before proceeding with the CPU instruction stream.
4.37.4.2.2
When writing to the address window associated with non-blocking transactions, the CPU can continue before the transaction is
completed. However, if there was a transaction ongoing when doing the 2nd write, the CPU is held until the first one is completed
before executing the 2nd one.
example.
As
are not affected by the change in the target caused by the previous transaction.
Freescale Semiconductor
Blocking
Write
Non-blocking
Write
Blocking
Read
Figure 96
STAA
LDAA
STAA
NOP
STAA
LDAA
STAA
NOP
illustrates, non-blocking writes have a performance advantage, but care must be taken that the following instructions
D2D activity
CPU activity
D2D activity
CPU activity
D2D activity
CPU activity
Blocking Writes
Non-blocking Writes
BLK_WINDOW+OFFS0 ; WRITE0 8-bit as a blocking transaction
#BYTE1
BLK_WINDOW+OFFS1 ; WRITE1 is executed after WRITE0 transaction is completed
NONBLK_WINDOW+OFFS0; write 8-bit as a blocking transaction
#BYTE1
NONBLK_WINDOW+OFFS1; executed right after the first
LDAA 0
STAA 0
STAA 0 LDAA # STAA 1
Figure 96
Figure 96
Figure 96. Blocking and Non-blocking Transfers.
shows the behavior of the CPU for a blocking write transaction shown in the following
Write Transaction 0
Write Transaction 0
shows the behavior of the CPU for a blocking write transaction shown in the following
Transaction 0
CPU Halted
CPU Halted
; load next byte
Halted
CPU
LDAA # STAA 1
STAA
MEM
NOP
Write Transaction 1
LDAA 1
Write Transaction 1
Transaction 1
CPU Halted
CPU Halted
Die-to-Die Initiator (D2DIV1)
NOP
NOP
MM912F634
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